There are instances in integrated circuit design where voltage level translators are needed to interface between circuits requiring different voltage levels. For example, many integrated circuits such as DRAMs operate in a voltage range &lt;4 volts, but require voltage swings &gt;4 volts to interface with external circuits or provide signals to other circuits included with the DRAM.
Two primary objectives of any voltage level translator are the reduction in time required to translate an input signal and the power requirements to complete the translation. A CMOS voltage translator described in U.S. Pat. No. 5,136,190 entitled "CMOS Voltage Level Translator Circuit" issued to Chern et al., addresses these two objectives. The Chern et al. patent describes a circuit which provides an interface between circuitry where control signals are between Vcc and V.s. to circuits using signals between Vcc' and V.s.. Specifically, the Chern et al. level translator works in integrated circuits where Vcc is &lt;4 volts and Vcc' is &gt;4 volts.
Although the Chern et al. patent provides a fast, efficient level translator, it fails to address interfaces requiring voltage swings between a supply voltage (Vcc) and some higher voltage (Vccp). That is, Chern et al. describes a level translator which translates an input voltage swing from ground (V.s.) to supply (Vcc) into an output voltage swing from V.s. to Vccp. This translator is relatively slow and wastes power in interfacing with a circuit which requires an input voltage swing between Vcc and Vccp. It can be seen that the transition time and power required to move the output voltage between V.s. and Vcc is an unnecessary use of resources.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an integrated circuit voltage level translator which can translate an input voltage signal into an output voltage signal where the minimum output voltage level is substantially equal to the maximum input voltage level.